Designing Energy Efficient Accelerators Through Neural Architecture Search

Abstract

 The exponential growth of deep learning workloads in embedded and edge computing environments has placed extraordinary demands on hardware efficiency, compelling researchers to seek principled methods for designing accelerators that simultaneously maximize computational throughput and minimize energy consumption. Neural architecture search (NAS) has emerged as a transformative paradigm for automating the discovery of model architectures, and its extension into hardware-aware co-design domains opens a compelling pathway toward accelerators that are not only functionally accurate but also energy-optimal. This paper presents a comprehensive framework for designing energy-efficient accelerators through hardware-aware NAS, integrating multi-objective optimization, dataflow-level energy estimation, and differentiable search strategies to navigate a joint hardware-software design space. We propose a co-exploration methodology that simultaneously optimizes the network topology, processing element (PE) array configuration, and memory hierarchy by incorporating energy and latency proxies directly into the search reward function. Experiments conducted on standard image classification benchmarks demonstrate that the proposed framework achieves accuracy competitive with manually designed architectures while reducing system-level energy consumption by up to 43% compared to baseline accelerator configurations. Our results further validate that dataflow-aware hardware parameterization yields substantially more energy-efficient accelerators than platform-agnostic search strategies, and that the use of analytical energy models as differentiable objectives enables scalable search without costly hardware prototyping.